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The parallel parametric test is an emerging strategy for wafer-level parametric testing that involves concurrent execution of multiple tests on multiple scribe line test structures. If offers the potential for increasing test throughput with existing test hardware, in response to market pressure on fabs to minimize test times. The figure illustrates the differences in the amount of time required to complete tests sequentially as compared to the same tests in parallel. ==Advantages== The potential advantages of parallel parametric testing include: * Cost of ownership advantages: By increasing throughput, parallel test decreases a system’s cost of ownership. The degree of throughput improvement has been documented between ×1.05 and ×3.9, depending on the existing test structure and pad layout as well as the specific combination of test structures within the TEG. * Test cell capacity advantages: Parallel testing can eliminate the need to add test cells or reduce the number of test cells in use by employing existing hardware more efficiently. * Impact on overall cost of test: Parallel testing can lower testing costs by reducing the number of test cells required, requiring fewer operators, reducing consumables costs and more. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Parallel parametric test」の詳細全文を読む スポンサード リンク
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